The present invention relates to a digital signal processor for use in image processing, speech processing, etc., and more particularly to a digital signal processor which is well suited to extract the maximum value from among a group of numerical values or the minimum value at high speed.
With a prior art digital signal processor, the maximum value has been found from among several numerical values stored in a data memory (DM) performing micro-instructions CMP (compare), LDA (load accumulator) and JMP (jump) as follows: ##EQU1## Here, instructions (1) signifies to load an accumulator (ACC) with n which is the least value. In instruction (2), B denotes the address of the memory in which the micro-instruction is stored, and the comparison between the value of the ACC and the numerical value of the address i of the DM is signified. An operation for the comparison is (value of ACC) -(value of DM, address i). instruction (3) signifies that, if the sign flag of a condition code register (CCR) is 0, that is, the result of the CMP operation is .gtoreq.0, the control jumps to address A. If the result of the CMP operation is &lt;0, the next instruction instruction (4) is executed. (4) signifies to load the ACC with the value of the DM, address i. instruction (5) signifies to increment the address of the DM by one, and instruction (6) signifies to jump to the address B. In this way, the maximum value of the several numerical values stored in the DM has been obtained.
On the other hand, the minimum value has been found as follows: ##EQU2## Here, instruction (7) signifies to load the ACC with the largest value. instruction (8) signifies that, if the sign flag of the CCR is 1, that is, (ACC) (DM.sub.ADR=i) &lt;0 , the control jumps to the address A.
Relevant to the processor of this type is digital signal processor TMS 32010 of Texas Instruments (TMS 32010 User's Guide 1984, TEXAS INSTRUMENTS).